Dynamic Random Access Memory (DRAM) cells are well known. A DRAM cell is essentially a capacitor for storing charge and an access transistor (also called a pass gate) for transferring charge to and from the capacitor. Data (1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. Because cell size affects chip density, size and cost, reducing cell area is one of the DRAM designer's primary goals.
One way to accomplish this density goal without sacrificing storage capacitance is to use trench capacitors in the cells. Trench capacitors can be formed by etching deep trenches in a silicon substrate and forming vertically orientated capacitors within each deep trench. Thus, the surface area required for the storage capacitor is dramatically reduced without sacrificing capacitance, and correspondingly, storable charge. In order to further decrease cell area, the access transistor may also be vertically orientated. The source of the vertical access transistor is a buried strap, which electrically connects the vertical access transistor to the underlying capacitor.
In typical memory array designs, the adjacent memory devices must be substantially separated to ensure that the buried strap regions of adjacent memory devices do not interact and cause buried strap leakage, where buried strap leakage disadvantageously reduces data retention time.
Referring to the prior memory array depicted in FIG. 1, buried strap leakage occurs between adjacent memory trench devices 14 (also referred to as memory cells) when the devices are positioned in close proximity to each other and allow for electrical interaction between the buried strap regions 15 of adjacent memory trench devices 14. Each memory trench device 14 typically comprises at least a trench capacitor 20 and a vertical transistor 10.
Referring to FIG. 2, in one prior memory array, buried strap leakage may be reduced by offsetting the buried strap regions 15 of each memory trench device 17, 18, where the offset increases the distance separating the adjacent buried strap regions 15. In prior memory arrays, the offset buried strap memory device 17 also comprises a recessed oxide collar 16, where the top surface of the recessed oxide collar 16 is at a greater depth from the top surface of the substrate 7 than the top surface of oxide collar 19 of the adjacent memory trench device 18.
Oxide collars 16, 19 are utilized to suppress parasitic leakage by controlling the threshold voltage of a parasitic transistor, which is formed between the buried strap 15 and the electrode material of the capacitor 20 in each trench device. In order to suppress parasitic leakage, the oxide collar 16, 19 must be greater than a minimum oxide collar length L1. Therefore, the recessed oxide collar 16 must be greater than the minimum oxide collar length L1 in order to suppress parasitic leakage in devices 17, 18.
Still referring to FIG. 2, memory trench devices 18 having oxide collars 19 that are not recessed are disadvantageously not optimized for maximum capacitance; because the greater length L2 of the oxide collar 19 effectively reduces the size of the underlying capacitor 20. In addition, the greater length of L2 causes increased external resistance of the filled trench poly and thus slows down memory read/write operation. Therefore, a tradeoff exists in prior memory array designs, where offsetting the buried strap 15 may suppress the loss of the storage charge due to buried-strap leakage, but at the expense of capacitor area, which reduces capacitance.
In view of the prior art mentioned above, a memory array comprising memory trench devices that are optimized for maximum capacitance and memory array density is needed.